In semiconductor integrated circuits, conductive contacts are formed so as to electrically connect multi-level interconnections to each other and/or between an interconnection and a substrate. FIG. 1 is a cross-sectional view showing a cell area and a peripheral circuit area of a conventional Dynamic Random Access Memory (DRAM). Reference numerals 80 and 90 represent the cell area and the peripheral circuit area, respectively.
Referring to FIG. 1, in the cell area 80, trench-type device isolation regions 4 defining an active area are formed in a substrate 2. A gate stack, including a gate insulating layer 6, a polysilicon layer 8, a silicide layer 10 and a capping insulating layer 12, is formed on the substrate 2 in which the device isolation regions 4 are formed. Gate spacers 16 are formed on sidewalls of the gate stack. Source/drain regions 19 including lightly doped impurity regions 14 and highly doped impurity regions 18 are formed in the active area adjacent to the gate stack. A first interlayer insulating layer 20 is formed on the substrate 2 that includes the gate stack having the spacers 16 formed on the sidewalls thereof. A bit line contact hole 22 is formed which passes through the first interlayer insulating layer 20. A bit line contact 29 including a barrier metal 26 and a tungsten layer 28 is formed within the bit line contact hole 22. A bit line 32a electrically connected to the bit line contact 29 is formed on the first interlayer insulating layer 20 in which the bit line contact 29 is formed. A second interlayer insulating layer 36 is formed on the bit line 32a and the first interlayer insulating layer 20. An opening 40 is formed to expose the source region 19 through the second interlayer insulating layer 36 and the first interlayer insulating layer 20. The opening 40 is filled with polysilicon to thereby form a contact plug 42. A capacitor including a lower electrode 44, a dielectric layer 46 and an upper electrode 48 is formed on the second interlayer insulating layer 36 in which the contact plug 42 is formed. A third interlayer insulating layer 50 is formed on the capacitor and the second interlayer insulating layer 36. A metal interconnection 62 including a barrier metal 56 and a tungsten layer 58 is formed on the third interlayer insulating layer 50.
In the peripheral circuit area 90, device isolation regions 4 defining an active area are formed on the substrate 2, and a highly doped impurity region 18 is formed in the active area. A lower interlayer insulating layer 20 is formed on the substrate 2. A lower contact hole 24 is formed through the lower interlayer insulating layer 20 to expose the highly doped impurity region 18. A lower contact 30 including a barrier metal 26 and a tungsten layer 28 is formed in the lower contact hole 24. An interconnection line 32b electrically connected to the lower contact 30 is formed on the lower interlayer insulating layer 20 in which the lower contact 30 is formed. An upper interlayer insulating layer 52 is formed on the interconnection line 32b and the lower interlayer insulating layer 20. An upper contact hole 54 is formed through the upper interlayer insulating layer 52 to expose the interconnection line 32b. An upper contact 60 and a metal interconnection 62, each of which includes a barrier metal 56 and a tungsten layer 58, are formed inside the upper contact hole 54 and on the upper interlayer insulating layer 52, respectively. In the peripheral circuit area 90, the highly doped impurity region 18, the interconnection line 32b and the metal interconnection 62 are electrically connected to each other via the lower contact 30 and the upper contact 60.
In the fabrication of the lower contact 30, the lower contact hole 24 exposing the highly doped impurity region 18 is formed on the lower interlayer insulating layer 20, and then the barrier metal 26 and the tungsten layer 28 are formed inside the lower contact hole 24 and on the first interlayer insulating layer 20. Thereafter, the resulting structure may be planarized using a Chemical Mechanical Polishing (CMP) process until a surface of the lower interlayer insulating layer 20 is exposed, thereby forming the lower contact 30. However, the CMP process may cause a well known dishing phenomenon such that the planarized surface is formed in a dish shape. Furthermore, the slurry used in CMP process may cause contamination and particle generation. Accordingly, in order to remove problems associated with contamination and/or particles during CMP process, extra cleaning process may be preformed.